/*
module clk_1k_1Hz(clk_1kHz,clk_1Hz);
	input clk_1kHz;
	output clk_1Hz;
	
	reg clk_1Hz = 0;
	reg[8:0] tem = 0;
	
	always @(posedge clk_1kHz)
	if (tem == 499)
		begin clk_1Hz <= ~clk_1Hz; tem <= 0;end
	else
		tem <= tem + 1;

endmodule

module clk_50MHz_1kHz(clk_50MHz,clk_1kHz);
	input clk_50MHz;
	output clk_1kHz;
	reg clk_1kHz = 0;
	
	reg[17:0] div = 0;
	
	always @(posedge clk_50MHz)
	begin
		if(div == 24999)
			begin div <= 0; clk_1kHz <= ~clk_1kHz; end
		else
			div <= div + 1;
	end

endmodule*/

module div (
	input clk_50M,
	output reg clk_1k = 0,
	output wire clk_1_posedge 
);
	reg [17:0] count1 = 0;
	reg [8:0] count2 = 0;
	reg clk_1 = 0;

	reg clk_1_DFF1;

	always @(posedge clk_50M) begin
		if (count1 == 24999) begin
			count1 <= 0;
			clk_1k = ~clk_1k;
		end
		else begin
			count1 <= count1 + 1'b1;
		end
	end

	always @(posedge clk_1k) begin
		if (count2 == 499) begin
			count2 <= 0;
			clk_1 <= ~clk_1;
		end
		else begin
			count2 <= count2 + 1'b1;
		end
	end

	always @(posedge clk_50M) begin
		clk_1_DFF1 <= clk_1;
		// clk_1_DFF2 <= clk_1_DFF1;
	end

	assign clk_1_posedge = clk_1 & ~clk_1_DFF1;

endmodule